The present invention relates to a voltage determination device capable of determining and identifying a level of a voltage, and a clock control device having the voltage determination device.
In general, in a clock, a motor generates a drive force to move a clock hand such as a second hand, a minute hand and an hour hand. A clock LSI (Large Scale Integration) is provided for controlling an operation of the clock hand. In order to move the clock hand with a minimum power, the clock LSI is configured to temporarily shut down a drive electric current supplied to the motor after a specific period of time (for example, a few milliseconds) after the clock LSI starts supplying the drive electric current to the motor. At this moment, when the clock hand moves, a counter electromotive voltage is generated. When the clock hand does not move, the counter electromotive voltage is not generated.
In the case that the clock hand does not move, it is necessary to supply the drive electric current to the motor for a prolonged period of time. Accordingly, in order to continuously control the operation of the clock hand, it is necessary for the clock LSI to determine whether the clock hand moves or not. As a method of determining whether the clock hand moves or not, there has been known a method of determining a level of the counter electromotive voltage generated in the motor.
In determining the level of the counter electromotive voltage, when a threshold value as a comparison reference becomes lower than a predetermined level, the level of the counter electromotive voltage may be erroneously determined due to a noise. More specifically, the clock LSI may determine that the clock hand moves even though the clock hand actually does not move. In this case, the clock LSI does not supply the drive electric current to the motor, so that the clock hand does not move. On the other hand, when the threshold value becomes higher than the predetermined level, the clock LSI may determine that the clock hand does not move even though the clock hand actually moves. In this case, the clock LSI supplies unnecessarily the drive electric current to the motor, so that power consumption increases.
Accordingly, in determining the level of the counter electromotive voltage, it is necessary to set the threshold value as the comparison reference at the most optimal level (within an acceptable range of the predetermined level). It should be noted that the optimal level may vary depending on the type of motor.
FIG. 8 is a circuit diagram showing a configuration of an NAND circuit 100 of a conventional voltage determination device. The NAND circuit 100 is disposed in a clock for determining the level of the counter electromotive voltage.
As shown in FIG. 8, the NAND circuit 100 includes P-channel type MOS field effect transistors 104 and 106 (referred to as PMOS transistors 104 and 106) and N-channel type MOS field effect transistors 108 and 110 (referred to as NMOS transistors 108 and 110). Further, the NAND circuit 100 includes a voltage line VDD to which a power source voltage is applied from a power source; an enable line EN to which a voltage is applied to selectively switch between an on state and an off state of each of the PMOS transistor 106 and the NMOS transistor 108; and an output terminal 112. A voltage corresponding to a comparison result obtained through comparing the level of the counter electromotive voltage with the threshold value is applied to the output terminal 112.
In the NAND circuit 100 with the configuration described above, when the power source thereof is shared with that of the clock LSI, according to the power source thus used (for example, a battery) and a motor 102, a gate length and a gate width of each of the PMOS transistor 104 and the NMOS transistor 108 are adjusted to control the threshold value.
As a size of the clock has been reduced, it is necessary to reduce the number of the batteries or the number of solar panels, thereby decreasing a voltage of generated power. Further, it may be necessary to use a rechargeable small secondary battery, thereby reducing the voltage of the power source of the clock LSI. Accordingly, it is necessary to adjust the threshold value in a wider voltage range of the power source. As a result, as the NAND circuit 100, when the power source thereof is shared with that of the clock LSI, the threshold value depends on the level of the voltage of the power source.
In the NAND circuit 100 of the conventional voltage determination device, when the threshold value is adjusted to a level near the voltage of the power source, it is necessary to significantly shift a ratio of abilities of following an electric current between the PMOS transistor 104 and the NMOS transistor 108.
More specifically, it is necessary to increase the gate width of the PMOS transistor 104, so that the ability of following the electric current in the PMOS transistor 104 is increased. Further, it is necessary to increase the gate length of the NMOS transistor 108, so that the ability of following the electric current in the NMOS transistor 108 is decreased. As a result, it is necessary to increase an area of the NAND circuit 100.
In order to reduce an area of a circuit, an NAND circuit 100A has been developed. FIG. 9 is a circuit diagram showing a configuration of the NAND circuit 100A of another conventional voltage determination device.
As shown in FIG. 9, the NAND circuit 100A includes a regulator 114 for maintaining the power source voltage applied to the voltage line VDD from the power source at a constant level. In the NAND circuit 100A, the power source voltage is maintained at the constant level to obtain a reference voltage, and the reference voltage is applied to a voltage line VSH. According, it is possible to apply the reference voltage to the voltage line ASH regardless of the power source voltage, so that the NAND circuit 100A utilizes the threshold value independent from the power source voltage.
When the NAND circuit 100A is adopted in the conventional voltage determination device, it is difficult to dispose a capacitance element with a sufficient capacity in the regulator 114, thereby making it difficult to further reduce the size of the clock LSI. When the capacitance element with the sufficient capacity is not disposed in the regulator 114, a through electric current is generated in the NAND circuit 100A when the counter electromotive voltage is applied to the gate terminal of each of the PMOS transistor 104 and the NMOS transistor 108. As a result, an output of the regulator 114 tends to rapidly drop, so that the threshold value is accordingly decreased.
In the description, the through electric current is referred to as an electric current flowing through a CMOS circuit (a switching circuit) formed of a combination of, for example, a PMOS transistor and an NMOS transistor (for example, refer to Patent Reference No. 1 and Patent Reference No. 2).    Patent Reference No. 1: Japanese Patent Publication No. 2001-044822    Patent Reference No. 2: Japanese Patent Publication No. 2007-249712
In the NAND circuit 100A shown in FIG. 9, when a signal level of a signal input from the motor 102 to the NAND circuit 100A as the counter electromotive voltage is switched from a low level to a high level, or from the high level to the low level, each of the PMOS transistor 104 and the NMOS transistor 108 becomes the on state for a specific period of time. As a result, the through electric current flows from the voltage line ASH to a ground line GND.
When the NAND circuit 100A shown in FIG. 9 is adopted in the conventional voltage determination device, the following problem may occur. The problem will be described below with reference to FIGS. 10 and 11. FIG. 10 is a circuit diagram showing a configuration of the regulator 114 of the NAND circuit 100A of the conventional voltage determination device. FIG. 11 is a graph showing a change in the threshold value of the NAND circuit 100A of the conventional voltage determination device.
As shown in FIG. 10, the regulator 114 includes an operation amplifier 116, a PMOS transistor 118, a constant electric current source 120, and a capacitor 122. In general, the capacitor 122 is disposed in the regulator 114 for releasing electric charges to switch the PMOS transistor 118 to the on state even when a load electric current is generated when the PMOS transistor 118 is in the off state, thereby delaying the switching operation.
In the regulator 114, when the load electric current does not exist on the side of the voltage line VAH, the PMOS transistor 118 is in the off state. When an excessive load electric current is generated on the side of the voltage line VAH due to the through electric current, since the PMOS transistor 118 is in the off state, an electric current is temporarily applied to the voltage line VSH according to a capacity accumulated in the capacitor 122.
In the regulator 114, as described above, it is difficult to secure a sufficient area for the capacitor 122, so that the capacity of the capacitor 122 is limited. Accordingly, after the capacity of the capacitor 122 is exhausted, until the PMOS transistor 118 is turned on, the voltage applied to the voltage line VSH from the regulator 114 is temporarily dropped as indicated with solid lines in FIG. 11. As a result, as shown in FIG. 11, the threshold value drops rapidly.
In order to solve the problems of the NAND circuit 100A described above, another configuration of the regulator 114 has been developed. FIG. 12 is a circuit diagram showing the configuration of the regulator 114 of the NAND circuit 100A of the conventional voltage determination device.
As shown in FIG. 12, the output terminal of the regulator is disposed outside as the terminal of the clock LSI, and a capacitor 124 with a sufficient capacity is connected to the output terminal. As indicated with hidden lines in FIG. 11, when the capacitor 124 is disposed on the output side of the regulator 114, it is possible to prevent the output of the regulator 114 from rapidly dropping, as well as prevent the threshold value from rapidly dropping. However, when the capacitor 124 is disposed on the output side of the regulator 114, it is necessary to increase a mounting area due to an increase in the number of the components.
In order to solve the problems of the NAND circuit 100A without disposing the capacitor 124, in the NAND circuit 100A shown in FIG. 9, an electric current load may be connected to the output side of the regulator 114, so that an electric current flows to the ground line GND all the time. Accordingly, it is possible to prevent the PMOS transistor 118 of the regulator 114 from switching temporarily from the on state to the off state. In this case, it is possible to prevent the mounting area from increasing due to the additional capacitor. However, it is difficult to prevent the power consumption from increasing.
As described above, when the conventional voltage determination device is provided for determining the level of the counter electromotive voltage for controlling the operation of the clock hand, the above problems tend to occur. As long as any device for determining a level of a target voltage uses a circuit having a switching circuit through which the through electric current flows (for example, an NAND circuit, an AND circuit, an OR circuit, and an NOR circuit), the above problems tend to occur.
In view of the problems described above, an object of the present invention is to provide a voltage determination device and a clock control device capable of solving the problems of the conventional voltage determination device. In the present invention, it is possible to accurately determine a level of a target voltage while minimizing an increase in a circuit size or power consumption.
Further objects and advantages of the invention will be apparent from the following description of the invention.